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Features
* * * * * * * * * *
1024 x 1024 Pixels with Memory Zone Up to 30 Images/Second Built-in Antiblooming Device Providing an Electric Shutter Function Pixel: 14 m x 14 m Image Zone: 14.34 x 14.34 mm2 Two Outputs at 20 MHz Each Readout Through 1 or 2 Outputs Possible Binning 2 x 2 Optical Shield Against Parasitic Reflexions and Stray Light A/R Window in 400 - 700 nm Bandwidth
Description
The TH7888A is particularly designed for high data rate applications (up to 30 pictures/second in 1024 x 1024 progressive scan format) in the medical and industrial fields. This area array image sensor consists of a 1024 x 1024 pixels (14 m x 14 m) image zone associated with a memory zone (masked with an optical shield). To increase the data rate, two separate outputs are provided, which can be used for parallel readout (the readout frequency is up to 20 MHz/output, leading to a total readout frequency of 40 MHz). These two outputs allow three readout modes (single or dual port). The TH7888A is designed with an antiblooming structure which provides an electronic shutter capability. Moreover, the 2 x 2 binning mode is available on this sensor, providing an image size of 512 x 512 pixels with 28 m x 28 m pixels. The TH7888A package is sealed with a specific anti-reflective window optimized in the 400 - 700 nm spectrum bandwidth on the sealed version.
Area Array CCD Image Sensor (1024 x 1024 Pixels with Antiblooming) TH7888A
Rev. 1999A-IMAGE-09/03
1
Figure 1. TH7888A General Sensor Organization
P1,2,3,4 M1,2,3,4 A
VA
1024 x 1024 Image Area
1024 x 1024 Memory Area
VDR
M
VDR
R
VDD1 VOS1 VS1 Bi-directional Serial Register VGS
R
VDD2 VOS2 VS2
L1-6
VGS
Functional Overview
Extra dark lines are provided for use as dark references or for smearing digital correction. Extra dark pixels are provided for dark line reference clamping. Each frame consists of 1056 video lines: * * * * * * * 1 dummy line 12 useful dark reference lines (with optical shield) 3 isolation lines 1024 useful lines 3 isolation lines 12 dark reference lines (with optical shield) 1 dummy line
Each video line is made up of 546 or 1058 elements, depending on the readout mode (single or dual port mode): * * * * * 12 inactive prescan elements 1 isolation prescan element 16 useful dark references (with optical shield) 5 isolation elements 512 or 1024 useful video pixels
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Pin Description
Figure 2. Pin Overview
AA P4 P2 VSS P3 P1 VSS VA M4 M2 VSS A M3 M1 M NC NC NC NC NC Y NC
B VS1 VOS2 VS2 VDP VSS VSS R L4 L1 L5 A VOS1VDD1VDD2 VDR VGS VSS VSS L3 L2 L6 10 9 8 7 6 5 Top View 4 3 2 1 A1 Index
Table 1. Pin Description
Pin Number Y9 AA9 Y10 AA10 Y5 AA5 Y6 AA6 Y4 B2 A2 A3 B3 B1 A1 A9 A8 B10 B8 B7 A6 A10 B9 B4 Symbol P1 P2 P3 P4 M1 M2 M3 M4 M L1 L2 L3 L4 L5 L6 VDD1 Output amplifier drain supply VDD2 VS1 Output amplifier source supply VS2 VDP VGS VOS1 Video outputs VOS2 R Reset clock Protection drain bias Register output gate bias Readout register clocks Memory to register clock Memory zone clocks Image zone clocks Designation
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Table 1. Pin Description (Continued)
Pin Number Y7 A7 AA7 A4, A5, B5, B6 Y8, AA4, AA8 Symbol A VDR VA VSS Substrate bias VSS Designation Antiblooming gate clock Reset bias Antiblooming diode bias
Geometrical Characteristics
Figure 3. Pixel Layout
A VA A A P1 P2 P3 P4 P1 A' Aperture 10 m 14 m A A VA
14 m
Figure 4. AA Cross Section
P1 P2 P3 P4 P1
14 m Transfer Direction
Potential Profile During Integration Time
Signal Charge for One Pixel
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Absolute Maximum Ratings*
Storage Temperature ..................................... -55C to +150C Operating Temperature.................................... -40C to +85C Thermal Cycling..........................................................15C/mn Maximum Applied Voltages: * Pins: Y9, AA9, Y10, AA10, Y5, AA5, Y6, AA6, Y4, B2, A2, A3, B3, B1, A1, B4, A6 ...........-0.3 V to 15 V * Pins: A9, A8, B10, B8, B7, A7, AA7 ..............-0.3 V to 15.5 V * Pin: Y7..............................................................-0.3 V to 12 V * Pins: A4, A5, B5, B6, Y8, AA4, AA8................... 0 V (ground) *NOTICE: *Stresses above those listed under absolute maximum ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Operating range defines the limits within which functionality is guaranteed. Electrical limits of applied signals are given in the operating conditions section.
Operating Precautions
Shorting the video outputs to any pin, even temporarily, can permanently damage the on-chip output amplifier.
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Operating Conditions
Table 2. DC Characteristics
Value Parameter Output amplifier drain supply Protection drain bias Reset bias Antiblooming diode bias Register output gate bias Output amplifier source supply Ground Notes:
(1)
Symbol VDD1, VDD2 VDP VDR VA VGS VS1(2), VS2 VSS
(2)
Min 14.5 14.5 14.5 14.5 2.2
Typ 15 15 15 15 2.5 0 0
Max 15.5 15.5 15.5 15.5 2.8
Unit V V V V V V V
1. Ground: note that the package metal back is grounded. 2. In dynamic mode, to avoid possible damage to the device, the addition of a Schottky diode is recommended (for example; diode reference BAR 43S) between VS1 and VSS ground in order to increase the potential on VS1, thus avoiding any direct mode diode current during clock transitions.
Readout Mode
The serial readout register is operated in a two-phase transfer mode. However, there are 6 separate command electrodes that should be connected differently, depending on the required readout mode. The following table gives the connections to be made for each mode.
Table 3. Readout Modes
Readout Modes Drive Clocks (Signals) L1 L2 1 Output, VOS 1 Pins B2, B3, B1 Pins A2, A3, A1 1 Output, VOS2 (Mirror Effect) Pins B2, A3, A1 Pins A2, B3, B1
2 Outputs (Parallel) Pins B2, B3, A1 Pins A2, A3, B1
Table 4. Timing Parameters
Definition Vertical transfer period Vertical transfer subdivision Rise time Fall time Readout register clock transition time Reset clock transition time Delay between output reset signal and reset clock Symbol TV TO tr tf t1 t2 td Comments Nominal value = 800 nm Tv = 8 x To For vertical transfer clocks (between 10% and 90% of the transition time)
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Timing Diagrams
Figure 5. Frame Timing Diagram
Integration Image # i + 1 Image Readout Memory Cleaning Period Fast Image to Memory Transfer
The following diagrams describe the 20 MHz readout frequency and 1.25 MHz vertical transfer frequency.
A P1 P2 P3 P4
1 2 1056 1056 Pulses
M = M1 M2 M3 M4
1 2 1056
L1 L2 R
See Figure 6
See Figure 7
Figure 6. Line Timing Diagram
7To
M = M1 M2 M3 M4
See Figure 9
5To 5To 3To 3To 3To 100 ns Min 3To 100 ns Min
L1 L2 R Vos1 (Vos2)
1 Note 1 12 13 Note 2 Note 3
1058 (or 546) Min
1 Note 1
12
Notes:
1. 12 pre-scan elements 2. 1 isolation element, 16 dark reference pixels, 5 isolation elements 3. 1024 useful video pixels (single output readout mode), 512 useful video pixels (dual output readout mode)
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Figure 7. Vertical Transfer During Image to Memory Zone Transfer
20 ns < Tf < To 100 ns Min 100 ns Min 20 ns < Tr < To
A
1 2 1056
P1 P2 P3 P4
M1 = M2 M2 M3 M4
See Figure 8
Figure 8. Transfer Period from Image Zone to Memory Zone (P and M for 1.25 Vertical Transfer Frequency FV = 1: Tv)
Tv = 800 ns tr 5 To tf 25 ns < Tr < To/3 25 ns < Tf < To/3 5 To To = 100 ns 3 To
P1 = M1
P2 = M2
P3 = M3
3 To 5 To
P4 = M4
To = Tv /8 3 To
Note:
Tr = Rise time Tf = Fall time To = Vertical transfer time subdivision Tv = Vertical transfer period.
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Figure 9. Output Diagram for Readout Register and Reset Clock 20 MHz Applications Crossover of Complementary Clocks (L1, L2). Between 30% and 70% of Maximum Amplitude.
50 ns 16 ns Min 16 ns Min
L1 t1 L2 12 ns Min R t2 t2 td VOS (1,2) Signal Level
Note: t1 = 7 ns typical t2 = 5 ns typical td = 8 ns typical delay time
t1
td
Reset Feedthrough
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Binning Mode Operation
In binning mode operation, the image is composed of 512 x 512 pixels (28 m x 28 m each).
Figure 10. Summation in the Readout Register of Two Adjacent Lines
15 T0
M1 M2 M3 M4
5 T0
3 T0 5 T0
5 T0 5 T0 3 T0 3 T0 3 T0
3 T0 3 T0 3 T0
5 T0 5 T0
M = M1
100 ns Min
L1 L2
Note: To view fall and rise times see Figure 8 on page 8
100 ns Min
Figure 11. Summation of Two Adjacent Pixels
L1
L2
Output Reset Frequency Divided by 2
R
VOS (1,2) Pixel i Useful Signal Pixel i + pixel i+1
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Exposure Time Reduction
The TH7888A provides an exposure time control (electronic shutter) function. The exposure time reduction is achieved by pulsing all the Pi gates to 0 V to continuously remove all the photogenerated electrons through antiblooming drain VA. Figure 12. Timing Diagram for Electronic Shutter
Frame Period 2 s
A P1
1 s
P2
P3 P4
Transfer
Obturation
Integration
Note:
To view fall and rise times see Figure 6 on page 7
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Table 5. Drive Clock Characteristics
Value Parameter Image zone clocks High level Low level Memory zone clocks High level Low level Memory register clocks High level Low level Antiblooming gate High level (integration) Low level (transfer) Reset gate High level Low level Readout register clocks High level Low level Symbol Min 7.5 0 Typ 8 0.5 8 0.5 9 0.5 4 0.5 12 2 9 0.5 Max 8.5 0.8 8.5 0.8 9.5 0.8 7 0.8 13 3 9.5 0.8 Unit V V V V V V V V V V V V Remarks Typical input capacitance 15 nF See Figure 12 Typical input capacitance 15.5 nF See Figure 12 Typical input capacitance 10 pF Typical input capacitance 14 nF See Figure 12 and Figure 14 Typical input capacitance 10 pF
P1, 1, 3, 4
M1, 2, 3, 4
7.5 0
M
8.5 0
A
3 0
R
10 0
L1, 2
8.5 0
1L
8 pF
2L
40 pF
40 pF
Maximum readout register frequency Maximum image zone to memory zone Transfer frequency
FH FV
20 1.7
- -
- -
MHz MHz
See Figure 9 See Figure 14
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Figure 13. Drive Clocks Capacitance Network
P2
3.3 nF 2.3 nF
P2
0.7 nF 0.5 nF 0.5 nF
P1
3.3 nF
A
2.3 nF
P3
2.8 nF
P1
0.7 nF
VA
P3
Substrate
P4
3.4 nF
P4 P1
4.4 nF
P2
2.2 nF
4.4 nF 2.2 nF 4.4 nF
4.4 nF 3.4 nF
P4
P3
3.9 nF
M1
4.4 nF
M2
3.2 nF
4.4 nF 3.2 nF 4.4 nF
4.4 nF 3.9 nF
M4
M3
Table 6. Static and Dynamic Electrical Characteristics
Value Parameter Output amplifier supply current Output impedance DC output level Output conversion factor Symbol IDD ZS VREF CVF 5.5 200 Min Typ 10 225 11 6 6.5 Max 15 250 Unit mA V V/eRemarks per amplifier
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Electro-optical Performance
*
General conditions: Temp = 25C (package temperature) Light source: 2854 K with 2 mm BG38 filter (unless specified) + F/3.5 optical aperture. 30 images per second mode (Ti = 33 ms) under typical operating conditions
* *
Readout mode: 2 outputs Values exclude dummy elements and blemishes
Table 7. Performance Description and Values
Value Parameter Output register saturation level Pixel saturation level Pixel saturation charge (electron per pixel) Responsivity at 640 nm Responsivity with BG38 filter Quantum efficiency at 640 nm Photo response non uniformity (1) Dark signal non uniformity (1) Average dark signal Symbol VSAT reg VSAT QSAT R QE PRNU DSNU VDS Min - 1.6 - - 3 - - - - - Temporal RMS noise in darkness (last line) Dynamic range Horizontal modulation transfer function at 500 nm Vertical charge transfer inefficiency (per stage) Horizontal charge transfer inefficiency (per stage) Notes: VN D MTF VCTI HCTI - - - - - Typ 2.6 1.9 320 6.5 4 15 0.4 0.28 2 4 200 80 70 - - Max - 3 - - - - 1.7 0.4 3 5.6 - - - 2.5.10-5 5.10-5 Unit V V keV/(J/cm2) V/(J/cm2) % %Vos mV mV mV V dB % - -
(2) (3) (4) (5) (6) (7) (1)
Remarks
See Figure 17
(8)
(9)
1. Pixel saturation (full well) as a function of vertical transfer frequency (see Figure 14 on page 15) and antiblooming adjustment (see Figure 15 on page 15). 2. After substraction of dark signal slope due to memory readout time. 3. First line level referenced from inactive prescan elements (12 samples). 4. Last line level referenced from inactive prescan elements (12 samples). 5. Measured with Correlated Double Sampling (CDS) including 160 V readout noise and dark current noise in general test conditions. 6. Saturation to RMS noise in darkness ratio. 7. At Nyquist frequency. 8. VSAT/2 measurement and 417 kHz vertical transfer frequency. 9. VSAT/2 measurement and 10 MHz horizontal transfer frequency.
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Figure 14. Saturation Level by Full Well with Antiblooming Off (A High = 0 V) Versus the Vertical Transfer Frequency
2
Saturation Voltage (V)
1.8
1.6
1.4
1.2 200
700
1200
1700
Vertical Transfer Frequency (kHz)
Figure 15. Saturation Level Limitation by the Antiblooming Effect on the Pixel (Typical Operating Conditions)
Inefficient Antiblooming Output Saturation Voltage (V)
Efficient Antiblooming
Inefficient Antiblooming
A High Level Clock (V)
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Figure 16. Smearing Effect
50
Smearing/Vsat(%)
40 30 20 10 0 0 2 4 6 8 10 % of Overilluminated Zone (Height) 100 x ESAT
10 x ESAT
NESAT = number of times ESAT TV V SMEARING ----------------------------- = N ESAT x ----- x H TI V SAT with ESAT = VSAT/responsivity (typical illumination conditions) * * Ti = integration time Tv = image to memory transfer time
Vertical Smearing Overillumination a
H b
Smearing Level
Vsat a,b Signal Line
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Figure 17. Spectral Response with A/R Window (Typical Case)
10
8
6
Responsivity V/(J/cm)
4
2
0 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100
Wavelength (nm)
Image Quality Grade
Blemish Clusters Columns General Conditions
Maximum area of 2 x 2 defective pixels. Less than 7 contiguous defects in a column. More than 7 contiguous defects in a column.
Room Temperature ...........................................................25C Frequency 30 images/s(under typical operating conditions)
Considered image zone ........................................ 1024 x 1024 Light Source 2854K with BG38 filter + F/3.5 optical aperture
At Vos = 0.7 Vsat
Type Blemishes/clusters Columns White > 20% Vos > 10% Vos Black || > 30% Vos || > 10% Vos
In Darkness
Blemishes/clusters Columns > 10 mV (*) > 5 mV (*)
(*) reference is Vo: average darkness signal
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Number of Defects
Total pixel numbers affected by blemishes and clusters .....100 Maximum number of clusters................................................10 Maximum number of columns.................................................5 : amplitude of video signal of defect with respect to mean output voltage Vos
Ordering Codes
TH7888AVRHRB: sealed version TH7888AVRHN: unsealed version
Figure 18. Ordering Information Key
1 TH788A 2 3 4 5 6 7 8 9 10 11
Technological Variants Temperature Range V: -40C to +85C Package Families R: Pin Grid Array (PGA) Image Grade H: High
Customer Specification Quality Assurance Level Standard Screening Nothing B = Mechanical Mask Package Variants N: Non-sealed Window R: Anti-reflective Window
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Package Outline
Figure 19. Package Drawing for 40-lead PGA
26.50 0.3
Pin No. = A1 Index
0,734 0,1
52.0 0.6
0.3 0.1
6.90 0.20
17.25 0.20
2.31 0.30
2.19 0.25
8
Y 3.04+0.04 -
0.5 X
Notes:
1. 2. 3. 4. 5. 6. 7. 8. 9.
All values are in mm. Black alumina 40-lead PGA package Black optical mask (only on sealed version) 400 nm - 700 nm AR coated window (R < 1% per side). Only on sealed version Metal back, (CuW - copper tungsten) gold plated. Electrically grounded (VSS) Optical center First useful pixel (readout through Vos1) Mechanical reference Photosensitive area dimensions 14,392(X) x 14,358(Y)
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Parameter Ztop Zbottom
Mechanical Distance 2.82 0.31 1.68 0.15
Optical Distance 2.31 0.30 2.19 0.25
Unit mm mm
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1999A-IMAGE-09/03 0M

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